FCBGA means Flip Chip Ball Grid Array, a packaging form with high-density I/O and high thermal performance. This product features high-density multilayer structure, large size and superfine traces, and SAP is mostly employed for the creation of circuit patterns. It applies basically on CPU, GPU, FPGA, ASIC and other HPC products.

1.High-density multilayer structure：1-2-1 ~ 10-2-10

2.Unit size：21mm×21mm ~ 77.5mm×77.5mm

3. Fine circuit: SAP, 9/12μm

4.Surface finish：ENEPIG+SOP / IT+SOP / OSP+SOP

Data center, smart driving, AI, HPC, etc.

SiP, System in Package, means packaging at the system level, where different functional chips or wafers and passive components are packed together to perform a basically complete system function. The purpose is to obtain a multifunctional, small-sized, high-performance and low-cost product. 

· Number of layers: 2-8 

· Trace width tolerance: tenting & etching: ±10μm; MSAP: ±5μm

· Surface finish: ENEPIG or ENIG, support WB and FC packaging

· Blind via dia./land: 60/100μm

· Layer shift, adjacent layer/any layer: 25μm max./50μm max.

· Support via on finger, plugging depression: -3~+5μm  

Consumer electronics, communication, computer, industrial automation, auto electronics, etc. 

Storage media to save programs and various data. Two most common semiconductor memories are DRAM and NAND. DRAM includes DDR, LPDDR and GDDR, and NAND includes eMMC, eMCP, UFP, uMCP and SSD as well as SD and MSD cards. 

· Number of layers: 2, 3 & 4

· Ultra-thin PCB: 2L 80μm, 3L 100μm, 4L 130μm

· Fine finger: 70/40/15μm (pitch/width/space)

·SR flatness: trace: 3μm, via: 5μm

·Blind via dia./land: 60/105μm

Smart phones, smart tablets, smart wearables and other consumer electronics, data communication, auto electronics, industrial control, etc. 

This type of substrates features array-arranged bump pads on the top side, and the chip face once flipped is directly connected to the substrate via bumping. As the signal transmission path is short and the chip back exposed, the thermal performance is excellent. The metal ball array in the bottom connects the product to PCB to realize product functions. 

· Number of layers: 2-8

· Trace width/space: 8/10μm (ETS) & 15/15μm (MSAP)

· Bump pitch: 130μm

· Typical surface finish: OSP/ENEPIG

· SM registration: ±12.5μm

· Support impedance

Smart phones, smart tablets, smart wearables and other consumer electronics, data communication, auto electronics, industrial control, medical devices, etc. 

This type of substrates features a bonding finger design for wire bonding on the top side. The chip is bonded to the substrate by epoxy, and the connection between the two is realized through wire bonding. The bottom side is designed with BGA pad, and the packaging product is connected to PCB via metal balls to realize product functions. 

· Number of layers: 2-8

· Trace width/space: 25/25μm

· Finger width/space: 90/40μm

· Strict SM flatness control ≤5μm

· Support busless design

Smart phones, smart tablets, smart wearables and other consumer electronics, auto electronics, industrial control, medical devices, etc. 

A major MEMS category including microphones and earphones which are designed with embedded capacitors, embedded resistors, cavities and contact pads. The sizes are mostly between1.5x1.5mm – 5x5mm  

Smart phones, smart tablets, smart wearables and other consumer electronics, auto electronics, etc.